1. Field of the Invention
This invention relates to a transfer of data, and particularly to a method of stabilizing one or more bus signals across an asynchronous or untimed interface without the use of a separate control signal for computer system data transfer.
2. Description of Background
In an SMP computer, such as the IBM® z Series® of mainframe computer systems manufactured by IBM, it is vitally important to maintain high levels or performance and interlocking. Many times, there are interfaces which are self-calibrating while others are timed to strict early/late timing criteria. However, self-calibrating logic can be costly in area. Asynchronous interfaces pose a problem as well due to extra handshaking signals that often cross between one side of the interface and another.
Many applications have data or controls that need to be sent over the bus asynchronously, where latency is not a big concern. Typically, metastability latches are added to help resolve possible transitions on signals. There is typically one control signal that is used for handshaking in one direction of the bus transfer. This signal is used to edge-trigger a sampling event. It is important that the data bus is stable before this signal is activated. Care must be taken to make sure that this control signal has more latency than the data bus. If not, the sampling could take place while the normal data bus is still transitioning.
While prior art techniques solve some of the problems that arise on asynchronous interfaces, there is a restriction that the control signal is separate from the data. Attempts to use the data bus to sample the data itself on an asynchronous interface can pose incorrect data samples due to not all the data bits being consistent on every cycle.